Semiconductor quantum dot device and method for forming a scalable linear array of quantum dots

ABSTRACT

An exemplary quantum dot device can be provided, which can include, for example, at least three conductive layers and at least two insulating layers electrically insulating the at least three conductive layers from one another. For example, one of the conductive layers can be composed of a different material than the other two of the conductive layers. The conductive layers can be composed of (i) aluminum, (ii) gold, (iii) copper or (iv) polysilicon, and/or the at least three conductive layers can be composed at least partially of (i) aluminum, (ii) gold, (iii) copper or (iv) polysilicon. The insulating layers can be composed of (i) silicon oxide, (ii) silicon nitride and/or (iii) aluminum oxide.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application relates to and claims priority from U.S. PatentApplication No. 62/328,691, filed on Apr. 28, 2016, the entiredisclosure of which is incorporated herein by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

This invention was made with government support under Grant No.W911NF-15-1-0149 awarded by the U.S. Army, Army Research Office. Thegovernment has certain rights in the invention.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to quantum computingarchitectures, and more specifically, to exemplary embodiments of anexemplary semiconductor quantum dot device and a method for forming ascalable linear array of quantum dots.

BACKGROUND INFORMATION

The density of transistors in integrated circuits has been followingMoore's law since its conception. (See, e.g., Reference 5). However, asthe size of transistors approaches the size of a single atom, the lawsof quantum physics play an increasingly dominant role in computerarchitectures, making it difficult for this trend to continue muchlonger. Despite this, the prospect of utilizing quantum mechanicalphenomena in information processing offers an opportunity to increasethe computational power of computers beyond what is known to be possibleon even the most ideal classical computer. (See, e.g., References 5 and6). Much like the classical computer depends on the robustness of thetransistor, functional quantum computers can require an on-chip physicalcomponent with reproducible properties that can be incorporated intolarge scale structures.

One of the leading candidates for the quantum analog of the transistoris the gate-defined, semiconductor, quantum dot. (See, e.g., References8 and 9). The spin state of an electron trapped in a quantum dot can bea beneficial physical system for storing quantum information. (See,e.g., References 10 and 12). Silicon (“Si”) in particular, with its weakhyperfine fields, small spin-orbit coupling and lack of piezoelectricelectron-phonon coupling, forms a “semiconductor vacuum” for spin states(see, e.g., Reference 13), and supports seconds-long electron spincoherence times. (See, e.g., Reference 14). However, the fabrication ofreliable and scalable Si-based quantum dots has proved challenging.Independent of the need for a pure spin environment, quantum dots shouldhave reproducible electrical properties for scaling. The large effectivemass of electrons in Si, along with the typically lower mobilities of Sitwo-dimensional (“2D”) electron gases, makes the fabrication of tightlyconfined, few-electron, quantum dots with reproducible propertiesdifficult. (See, e.g., Reference 15).

Early quantum dot gate architectures were fabricated on doped GalliumArsenide/Aluminum Gallium Arsenide (“GaAs/AlGaAs”) substrates in whichconduction electrons are provided by a global dopant layer, and can beconfined to the GaAs/AlGaAs quantum well (“QW”) interface forming atwo-dimensional electron gas (“2DEG”). In these doped structures, bydefault, the 2DEG is filled with conduction electrons. Therefore, gatedesigns attempted to isolate a single conduction electron by fabricatinggate electrodes in a corral pattern that could potentially create acircular barrier by applying negative voltages on the gates to depletethe 2DEG directly beneath the gates. (See, e.g., Reference 1). Devicesutilizing this type of gate pattern have been referred to as depletionmode devices.

Depletion mode devices have been very successful in demonstrating thecriteria for quantum computation (see, e.g., Reference 2), and are stillin widespread use throughout the quantum dot community. However, thereare major drawbacks to depletion mode devices with respect to control ofthe confinement potential and scaling. The gate patterns in depletionmode devices likely have the most control over the electrostaticpotential surrounding the dot, rather than having direct control overthe region of space where the electron wavefunction resides. Thisinability to control the electron wavefunction has led to a largevariety of depletion mode gate designs, most of which do not provide astraightforward path for scaling to tens or hundreds of quantum dots.

The use of the quantum dots in quantum computing architectures generallydepends on the ability to control the confinement potential of thequantum dot, and more specifically the ability to control the physicallyrelevant parameters of the quantum dot, (e.g., tunnel coupling and theelectrochemical potential). However, depletion mode devices have verylimited control over the confinement potential. Simulations of thedepletion mode quantum dot devices have shown that the resultingconfinement potential can be much smaller than the gate dimensions. (Seee.g., Reference 3). Because of such a situation, neighboring gatesusually have a similar effect on the dot's tunnel couplings andelectrochemical potential, and often it's not possible in depletion modedevices to tune the tunnel couplings and electrochemical potential tothe desired values without going to such extreme voltages thatdielectric breakdown occurs in the device. (See, e.g., Reference 4).

Quantum computing architectures require that the gate pattern bescalable. This can imply that the gate pattern must consist of unitcells that can be repeated over and over to create larger arrays. Mostof the gate patterns which have been developed thus far do not consistof unit cells, and the gate patterns for double and triple quantum dotsdo not resemble the gate patterns for single quantum dots. This can makeit unclear how to take existing gate patterns and extend (e.g., scale)them to tens or hundreds of quantum dots.

Thus, it may be beneficial to provide an exemplary semiconductor quantumdot device, which can overcome at least some of the deficienciesdescribed herein above.

SUMMARY OF EXEMPLARY EMBODIMENTS

To that end, in order to overcome at least some of the deficienciesdescribed herein above, an exemplary quantum dot device can be provided,which can include, for example, at least three conductive layers and atleast two insulating layers electrically which insulate the conductivelayers from one another. One of the conductive layers can be composed ofa different material than the other two of the conductive layers. Theconductive layers can include or be composed of (i) aluminum, (ii) gold,(iii) copper and/or (iv) polysilicon. As an alternative, the conductivelayers can be composed at least partially of (i) aluminum, (ii) gold,(iii) copper and/or (iv) polysilicon. The insulating layers can becomposed of (i) silicon oxide, (ii) silicon nitride or (iii) aluminumoxide.

In some exemplary embodiments of the present disclosure, the conductivelayers can be composed of a metallic material having a purity rate ofover 90% (e.g., 99.9%). Each of the conductive layers can have athickness of less than about 200 nm, or even less than about 100 nm.Each of the insulating layers can have a thickness of less than about 10nm, or even less than about 4 nm. Each of the insulating layers can bein direct contact with at least two of the conductive layers.

In certain exemplary embodiments of the present disclosure, theexemplary quantum dot device can include at least three furtherconductive layers and at least two further insulating layerselectrically insulating the further conductive layers, where the furtherconductive layers and the at least two further insulating layers can beelectrically coupled to the conductive layers and the insulating layers.

In some exemplary embodiments of the present disclosure, the conductivelayers can be fabricated or provided on a semiconductor substrate, whichcan include, for example, (i) a silicon/silicon-germanium (Si/SiGe)substrate, (ii) a silicon dioxide on silicon substrate and/or (iii) aGaAs/AlGaAs heterostructure. A first one of the conductive layers can beconfigured to operate as a screening layer, a second one of theconductive layers can be configured to accumulate electrons in atwo-dimensional electron gas (“2DEG”) and a third one of the conductivelayers can be configured to tune a barrier(s) between regions of the2DEG accumulated by the second conductive layer. Each of the conductivelayers can have a different voltage level applied therethrough.Connections between the conductive layers and the insulating layers cancause single electrons to be shuttled through quantum dots of the deviceusing voltage pulses.

According to further exemplary embodiments of the present disclosure, aquantum dot device can be provided which can comprise a repeatingquantum dot cell structure having repeated cells. For example, each ofthe repeated cells can be electrically connected to another one of therepeated cells which is adjacent thereto. Electrically-connected quantumdots of at least one of the repeated cells can be provided in a nearestneighbor configuration. At least one of the repeating cells can includeat least two quantum dots (or at least three quantum dots). Each of therepeating cells can include at least three conductive layers and atleast two insulating layers electrically insulating the at least threeconductive layers from one another. The charge state of each of therepeating cells can be (i) measurable, (ii) readout using a quantumpoint contact, (iii) readout using a charge sensor quantum dot, and/or(iv) readout through the use of a radio frequency measurement.Connections between the connected cells can cause single electrons to beshuttled through quantum dots of the device using voltage pulses.

According to a further exemplary embodiment of the present disclosure, aquantum dot arrangement can be provided, which can include at leastthree quantum dot devices, where each of the quantum dot devices can beelectrically connected to an adjacent one of the quantum dot devices. Atleast one of the quantum dot devices can be provided in a nearestneighbor configuration with another one of the quantum dot devices. Thequantum dot devices can include at least seven quantum dot devices, orat least nine quantum dot devices.

In some exemplary embodiments of the present disclosure, each of thequantum dot devices can include at least three conductive layers and atleast two insulating layers electrically insulating the at least threeconductive layers from one another.

These and other objects, features and advantages of the exemplaryembodiments of the present disclosure will become apparent upon readingthe following detailed description of the exemplary embodiments of thepresent disclosure, when taken in conjunction with the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects, features and advantages of the present disclosure willbecome apparent from the following detailed description taken inconjunction with the accompanying Figures showing illustrativeembodiments of the present disclosure, in which:

FIG. 1 is an illustration of a cross section of the exemplary Si/SiGesubstrate showing the Si quantum well, SiGe spacer and Si cap accordingto an exemplary embodiment of the present disclosure;

FIGS. 2A to 2C are exemplary diagrams of three exemplary layers of thegate pattern according to an exemplary embodiment of the presentdisclosure;

FIGS. 3A and 3B are exemplary diagrams illustrating the first and secondlayers shown in FIGS. 2A-2C overlaid on each other as well as theresulting two-dimensional electron gas in the quantum well according toan exemplary embodiment of the present disclosure;

FIG. 4 is a diagram illustrating the use of timed pulses to shuttle anelectron through the main array of quantum dots according to anexemplary embodiment of the present disclosure;

FIG. 5A is an exemplary false-color scanning electron microscope imageillustrating the overlapping gate architecture according to an exemplaryembodiment of the present disclosure;

FIG. 5B is an image produced by an exemplary COMSOL simulation, and agraph illustrating the confinement potential, according to an exemplaryembodiment of the present disclosure;

FIG. 6A is an exemplary plot illustrating a charge stability diagram ofquantum dot 9, according to an exemplary embodiment of the presentdisclosure;

FIG. 6B is an exemplary graph illustrating the addition of energyplotted as a function of electron number N for dots 4, 6, 8 and 9,according to an exemplary embodiment of the present disclosure;

FIG. 6C is a set of exemplary diagrams illustrating pulsed gatespectroscopy, according to an exemplary embodiment of the presentdisclosure;

FIG. 6D is an exemplary diagram illustrating an orbital excited statebeing visible for dot 9 according to an exemplary embodiment of thepresent disclosure;

FIG. 7A is an exemplary image illustrating a Coulomb blockade peak forsensor dot 3, according to an exemplary embodiment of the presentdisclosure;

FIG. 7B is an exemplary graph illustrating g_(s3) measured at the dashedlines from FIG. 7A, according to an exemplary embodiment of the presentdisclosure;

FIG. 7C is an exemplary graph illustrating ΔV_(s3) measured for dots 2through 8, according to an exemplary embodiment of the presentdisclosure;

FIG. 7D is an exemplary diagram illustrating that the power lawdependence can be qualitatively understood as the field of a dipole thatis formed by an electron in the quantum well and its positive charge,according to an exemplary embodiment of the present disclosure;

FIG. 8A is an exemplary graph illustrating the current through sensordot 3 as a function of V_(P8) and time near the charge transitionaccording to an exemplary embodiment of the present disclosure;

FIG. 8B is an exemplary graph illustrating the time series extractedfrom the data shown in FIG. 8A at positions shown by the dashed lines inFIG. 8A, according to an exemplary embodiment of the present disclosure;

FIG. 8C is an exemplary graph showing the time-averaged quantum dot 8occupation extracted from the data shown in FIG. 8A, and plotted as afunction of V_(P8), according to an exemplary embodiment of the presentdisclosure;

FIG. 9A is an exemplary graph showing a time series of the currentthrough sensor dot 3, with dot 8 configured at the charge transition,according to an exemplary embodiment of the present disclosure;

FIG. 9B is an exemplary graph illustrating a histogram of a one secondtime series showing two Gaussian peaks, according to an exemplaryembodiment of the present disclosure;

FIG. 9C is an exemplary graph illustrating the signal-to-noise ratioplotted as a function of the filter cutoff frequency, according to anexemplary embodiment of the present disclosure;

FIG. 10A is an exemplary diagram illustrating a single electron spinthat is measured by aligning the spin states relative to the Fermi levelof a source electrode, according to an exemplary embodiment of thepresent disclosure;

FIG. 10B is an exemplary graph of single shot traces, according to anexemplary embodiment of the present disclosure;

FIG. 10C is an exemplary graph illustrating how the spin up probabilityP_(↑) decays exponentially with t_(wait), according to an exemplaryembodiment of the present disclosure;

FIGS. 11A and 11B are exemplary graphs illustrating how dots 6 and 7,and dots 8 and 9, are simultaneously tuned up to for two double quantumdots (“DQDs”), according to an exemplary embodiment of the presentdisclosure;

FIG. 11C is an exemplary graph illustrating that the capacitiveinteraction between the two DQDs can be extracted by measuring thequadruple dot charge stability diagram, according to an exemplaryembodiment of the present disclosure;

FIG. 12 is an exemplary method for fabricating a quantum dot device,according to an exemplary embodiment of the present disclosure; and

FIG. 13 is an illustration of an exemplary block diagram of an exemplarysystem in accordance with certain exemplary embodiments of the presentdisclosure.

Throughout the drawings, the same reference numerals and characters,unless otherwise stated, are used to denote like features, elements,components or portions of the illustrated embodiments. Moreover, whilethe present disclosure will now be described in detail with reference tothe figures, it is done so in connection with the illustrativeembodiments and is not limited by the particular embodiments illustratedin the figures and the appended claims.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Thus, as described herein, an exemplary quantum dot device can beprovided, which can be or include an aggressively scaled semiconductorquantum dot device. The exemplary device can include 12 quantum dots,nine of which can be arranged in a linear array, and three that can beused as sensitive charge detectors. The exemplary device according to anexemplary embodiment of the present disclosure can utilize anoverlapping metallic gate architecture to facilitate tight electronicconfinement (see, e.g., Reference 16), while an undoped heterostructurecan provide a clean, high mobility interface (see, e.g., Reference 17)for the formation of well-behaved quantum dots with reproduciblecharacteristics.

The exemplary gate pattern can be fabricated or otherwise placed on topof a semiconductor substrate (e.g., an undoped silicon/silicon-germanium(“Si/SiGe”) substrate). A cross section of the exemplary substrate 100is shown in FIG. 1. A pure Si QW layer 110 can be grown on top of a SiGesubstrate 105, followed by a SiGe spacer layer 115. A thin Si cap layer120 can be used to protect the SiGe spacer layer 115 during furtherprocessing. Ohmic contacts can be made to the QW using, for example,locally doped regions of the wafer. Various other suitable semiconductorsubstrates (e.g., quantum well structures) can be used, which caninclude, for example, silicon dioxide on silicon and/or AlGaAs/GaAsheterostructures.

The exemplary gate pattern (e.g., quantum dot) can include, for example,three conductive (e.g., metallic) layers. Exemplary suitable materialsfor the conductive layers can include, but are not limited to, aluminum,gold, copper and/or polysilicon. The exemplary layers can be composedalmost entirely of the respective material (e.g., having a 99.9%purity). Alternatively, the conductive layers can be composed partiallyof the respective material. Each such layer can be exposed to anoxygen/argon mixture directly, after metallization, in vacuum in orderto facilitate an insulating layer (e.g., an oxide layer) to form on theoutside of the metal. This exemplary layer of oxide can electricallyisolate each layer from further layers of metal. The exemplary gatepattern of the first layer is shown in FIG. 2A. The first layer of metal205 can operate as a screening layer. Such screening layer can define asingle-dimensional channel 210 that can contain the array of quantumdots, as well as adjacent transport channels 215 that can contain chargesensing quantum dots. The exemplary second gate layer 220, which can beon top of or adjacent to the first layer, is shown in FIG. 2B, and canbe used to accumulate electrons. These exemplary gates can be held atrelatively positive voltages, and can accumulate electrons underneaththem through openings 215 in the screening layer. Gate electrodes ineach layer can have their own respective voltage (e.g., voltage level)applied therethrough. The exemplary third layer, which can be on top ofor adjacent to the second layer, is shown in FIG. 2C, can containbarrier gate electrodes 225 that can be used to tune the barriersbetween regions of the two-dimensional electron gas (“2DEG”), which canbe accumulated by the second layer.

According to certain exemplary embodiments of the present disclosure, anexemplary thickness of the conductive layers can be about 200 nm or less(e.g., within 5%-10% of such number). According to addition exemplaryembodiments of the present disclosure, the exemplary thickness of theconductive layers can be about 100 nm (e.g., within 5%-10% of suchnumber)). An exemplary thickness of the insulating layer can be about 10nm or less (e.g., within 5%-10% of such number)). In further exemplaryembodiments of the present disclosure, the exemplary thickness of theinsulating layer can be about 4 nm or less (e.g., within 5%-10% of suchnumber)). Various suitable exemplary insulating materials can be used,which can include, for example, silicon oxide, silicon nitride and/oraluminum oxide.

The second and third layers of the exemplary device according to theexemplary embodiment of the present disclosure can have or providecontrol over regions of the 2DEG, which can be much smaller than theirfull lithographic dimensions. This can be achieved by screening. Gatesin the second layer can likely affect only the 2DEG through the openingin the first layer. This exemplary configuration can reduce the regionwhich they control to x1 by y, as illustrated in the diagram of FIG. 3A.Gates in the third layer can be restricted to even smaller gaps in thefirst two layers such that the region of the 2DEG, which they havecontrol over, can be x2 by y. By utilizing screening in such exemplarymanner, it is possible to provide each gate with a more local control ofthe confinement potential. Thus, there can be less cross capacitance.This reduced cross capacitance can make it significantly easier to tunethe physically relevant parameters of the dot.

The charge occupation of the exemplary quantum dots can be read outthrough the adjacent charge sensing quantum dots. The exemplarylocations of the dots 305 in the main array, and the sensor dots 310,are illustrated in FIG. 3B. For example, one charge sensor can be placedfor every three quantum dots in the main array. The conductance throughthe charge sensing quantum dots will exhibit Coulomb blockade peaks. Bysetting the conductance on the side of one of these Coulomb blockadepeaks, changes in the charge state of nearby quantum dots in the mainarray can create a change in the conductance through the charge sensor.From this, it can be possible to track the movement of charge throughthe main array of quantum dots.

The exemplary manner in which the number of gates can scale with thenumber of quantum dots can be considered for the exemplary scaling. Forexample, each dot in the main array of dots can be defined by oneplunger gate and two barrier gates. Each barrier gate can be sharedbetween adjacent dots, except for the first and last dot of the arraywhich each can have a barrier separating it from the reservoirs oneither side of the array. Therefore, the number of plunger and barriergates can scale as 2N+1, with N equal to the number of dots in thearray. It can be beneficial that the number of gates, and the length ofthe array, scale linearly with N. This can ensure that it can befeasible to scale to a large N without needing a fundamental designchange above some number of quantum dots.

This exemplary device described herein can be used to shuttle singleelectrons through the 2DEG in a controlled manner. This can be achievedby applying a series of timed voltage pules 405 to the gates asillustrated in FIG. 4. For example, the voltage pulses 405 hit eachquantum dot consecutively leading to sequential tunneling of theelectron through each quantum dot. The ability to shuttle single chargesthrough arrays of quantum dots can be used to move information through aquantum computer.

Exemplary Linear Gate Architecture

A false-colored scanning electron microscope (“SEM”) image of the deviceis shown in FIG. 5A, and a COMSOL simulation of the electron density nin the plane of the quantum well is shown in FIG. 5B. Tight electronicconfinement can be achieved, for example, using an overlapping aluminumgate architecture. (See, e.g., Reference 16). As shown in such drawings,in the upper half of the exemplary device, two sets of aluminum gateelectrodes, with a pitch of about 100 nm, can be interleaved to form alinear array of 9 quantum dots. A plunger gate can control the chemicalpotential of each quantum dot 505, while barrier gates can control thetunnel coupling of adjacent dots 510. An aluminum screening layer canrestrict the action of the tuning gates to a one-dimensional (“1D”)channel. (See, e.g., Reference 16). High sensitivity single electroncharge detection can be achieved using three single dot charge sensorsdefined in a second one-dimensional channel that can be formed in thelower half of the device 515.

The scalability of the exemplary device can be illustrated from itsrepeating unit cell structure. Each exemplary unit cell can consist ofthree quantum dots and a charge sensor. The exemplary device can beconstructed, for example, by concatenating three of these unit cells.Scaling to arrays of arbitrary length can be achieved by addingadditional unit cells. The overlapping gate architecture demonstratedhere has roughly about 4.5 times the areal density of a widely-useddouble dot depletion mode gate pattern; 9 dots and 3 charge sensors werefit in an area of ˜1.5 μm², the same area as a GaAs double quantum dotand its two quantum point contact charge detectors. (See, e.g.,Reference 2).

Exemplary Characterization of the 9 Dot Array

Scaling to large arrays of quantum dots can benefit from uniform andreliable single quantum dot characteristics. For example, three figuresof merit can be used to characterize the reproducibility of the lineararray: the lever arm a, charging energy E_(c), and orbital excited stateenergy E_(orb). A single quantum dot can be formed under each plungergate, with the neighboring quantum dots tuned to the many electronregime and extract a, E_(c) and E_(orb) for each dot using a combinationof transport measurements, charge sensing and pulsed gate spectroscopy.

Lever arms can be extracted from transport measurements of Coulombdiamonds at the N=0 to 1 transition, where N can refer to the number ofelectrons in the dot. The charge state of each dot can be read out bymeasuring the conductance through the nearest single dot charge sensor.As an example, the diagram of FIG. 6A shows the charge stability of aquantum dot formed under plunger gate P9. As shown in FIG. 6A, thederivative of the charge sensor conductance, dg_(S3)/dV_(P9), can beplotted as a function of V_(P9) and V_(B10). The lack of chargetransitions for low values of V_(P9) can indicate that dot 9 (e.g.,element 605) has been emptied of free electrons, reaching N₉=0 chargeoccupancy. Addition voltages for dot 9 can be extracted along thevertical dashed line 605 shown in FIG. 6A, and converted into additionenergies, E_(add), using ∝. These addition energies are plotted in thegraph 610 shown FIG. 6B. For example, the addition energies for dots 4,6 and 8 (e.g., elements 615, 620 and 625, respectively) are shown inFIG. 6B. The increase in E_(add) at the N=4 to 5 charge transition canbe attributed to shell filling of the low lying spin and valley degreesof freedom. (See, e.g., References 18 and 19).

Pulsed gate spectroscopy can be performed in each dot at the N=0 to 1charge transition in order to extract the orbital excited state energyE_(orb). (See, e.g., References 20 and 21). An about 500 Hz square wave,with peak-to-peak amplitude, V_(pulse), can be added to the dc plungergate voltage to repeatedly load and unload an electron onto the dot. Fora small V_(pulse), only the ground state can be pulled below the Fermilevel of the lead (e.g., see diagram 630 shown in FIG. 6C) and anelectron tunnels onto the dot with a rate Γ_(g). When the pulseamplitude can exceed V_(orb), the electron can load into either theground state or the first excited state (e.g., diagram 635 shown in FIG.6C). The effective loading rate can be increased due to the contributionfrom the excited state Γ_(e), and can be visible in the charge sensingdata. The change in conductance due to the ground state creates thesloped line 640 in FIG. 6(D). The region marked by the blue square 645in FIG. 6(D) corresponds to the configuration of 630, where only theground state is pulsed below the Fermi level, while the region marked bythe green circle 650 corresponds to the configuration of 635, where boththe ground state and excited states are pulsed below the Fermi level.The transition from region 645 to 650 occurs at a voltage V_(orb) abovethe ground state line 640. From these data, an orbital excited stateenergy E_(orb)=αV_(orb)=3.4 me V can be extracted for dot 9.

Similar characterization can be performed on dots 1-8, and the resultsare summarized in Table I below. The averaged figures of merit can beα=0.13±0.01 meV/mV, E_(c)=6.9±0.7 meV, and E_(orb)=3.0±0.5 meV. Theseexemplary charging energies can generally be larger than those obtainedwith other device designs in Si/SiGe due to the tight confinementpotential generated by the overlapping gate architecture. For example,depletion mode devices achieved charging energies of less than about 2meV (see, e.g., Reference 22), while enhancement mode architectures haveyielded charging energies close to about 5 meV. (See, e.g., Reference19). Moreover, the large orbital excited state energies can becomparable to those measured in GaAs devices, which has an effectivemass that can be nearly three times smaller than Si. (See, e.g.,Reference 9).

TABLE I Lever-arm conversion between gate voltage and energy α, chargingenergy E_(c), and orbital excited state energy E_(orb) for each of thenine dots in the linear array. Dot α (meV/mV) E_(c) (meV) E_(orb) (meV)1 0.14 6.6 2.7 2 0.13 6.1 2.6 3 0.11 5.6 2.1 4 0.14 7.3 3.3 5 0.14 7.23.3 6 0.14 7.1 3.0 7 0.14 7.7 3.5 8 0.14 7.1 3.4 9 0.13 7.2 3.4Exemplary Sensitive Charge Detection

An exemplary criteria for quantum information processing can be highfidelity qubit readout. For both single shot readout of an individualspin (see, e.g., References 23 and 24), and spin-to-charge conversion indouble (see, e.g., Reference 2) and triple quantum dot qubits (see,e.g., Reference 25), this can translate to a need for a high fidelitycharge state readout. The exemplary device can sensitively detect chargeusing the exemplary charge sensor array. The three sensor dots canprovide good coverage over the entire 9 dot array.

In order to characterize the charge sensor performance, the shift in acharge sensor Coulomb blockade peak due to a change in the chargeoccupancy of a nearby dot in the linear array can be measured. Forexample, FIG. 7A shows a graph illustrating the conductance throughcharge sensor 3, g_(S3), as a function of V_(P8) and V_(S3). A Coulombblockade peak is visible in the sensor dot conductance, and it abruptlyshifts each time an electron can be added to quantum dot 8. For example,peak 730 in FIG. 7(B) is plotting the peak taken at the position of adashed line 705 in FIG. 7(A), and peak 735 in FIG. 7(B) is plotting thepeak taken at the position of a dashed line 710 in FIG. 7(A). These twoCoulomb blockade peak are on either side of the N₈=0 to 1 chargetransition. A peak shift of ΔV_(S3)=0.26 mV at the N₈=0 to 1 chargetransition can be measured from the displacement of the two peaks 730,735. The shift in the charge sensor 3 Coulomb blockade peak position canalso be measured for dots 2-7, and is plotted in the graph shown in FIG.7C as a function of the geometric distance, d, between each dot and thesensor dot. The shift can fall off rapidly as 1/d³.

Predictions for the shifts in the sensor dot Coulomb blockade peakposition can be obtained by computing the capacitances of the device. Athree-dimensional (“3D”) model of the device can be constructed based onthe wafer growth profile and lithographic gate dimensions, representingthe dots as metallic cylinders with a radius of about 12 nm and a heightof about 5 nm. The capacitances of the exemplary device can be computedusing a fast-multipole-moment solver (e.g., FastCap). (See, e.g.,Reference 26). The expected shift can be computed or otherwisedetermined from the simulated capacitances using

${{\Delta\; V_{S\; 3}} = \frac{e^{2}C_{m}}{C_{p}C_{t}}},$where C_(m) can be the mutual capacitance between the sensor dot and thesingle-electron dot, C_(p) can be the capacitance between the sensor dotand its plunger gate, and C_(t) can be the total single-electron dotcapacitance. (See, e.g., Reference 27). The computed/determined shiftcan scale as ΔV_(S3)(d)∝1/d^(2.96), and can compare with theexperimental data. (See, e.g., line 740 shown in FIG. 7C).

As in the case of a parallel plate capacitor, the capacitance can beexpected to scale as 1/d. However, the overlapping gate architecturecovers nearly the entire Si/SiGe heterostructure with metal, resultingin a significant amount of screening. The impact of this screening canbe illustrated using the diagram shown in FIG. 7D. An electron 745trapped in a quantum dot can induce a positive image 750 charge in thegate metal above. The resulting electric field due to the electron andits image charge can be that of a dipole, which can fall off with a 1/r³dependence.

Exemplary Real-Time Charge Detection

The ability to resolve real-time charge dynamics can facilitate thestudy of fundamental physical phenomena at the level of a singleelectron. (See, e.g., References 28 and 26). It can also enable asingle-shot readout of single electron spin states (see, e.g.,References 23 and 24), and the discrimination of two-electron singletand triplet spin states. (See, e.g., Reference 2). The exemplary devicecan have a high sensitivity charge detection through the observation ofreal-time tunneling events. (See, e.g., References 30 and 31). Through aquantitative analysis of the charge sensor response, a chargesensitivity of 8.2×10⁻⁴ e/√{square root over (H_(z))} can be extracted.

FIG. 8A shows a color-scale plot of the current 1 through sensor dot 3as a function of time, for a range of plunger gate voltages V_(p8) withdot 8 tuned up near the N₈=0 to 1 charge transition. Five time series(e.g., element 805) extracted from this data set are plotted in thegraph shown in FIG. 8B. The lowest time-series shown in FIG. 8B wasacquired with V_(P8)=661.12 mV. Thus, the exemplary dot can be emptynearly all of the time. With V_(P8) slightly increased, the currentshows signatures of real-time single electron tunneling events, andswitches between two levels corresponding to the N₈=0 and 1 chargestates. The dwell time in the N₈=1 charge state increases withincreasing V_(P8) Using a threshold to discriminate between the chargestates, the time-averaged occupation of dot 8,

N₈

, can be plotted as a function of V_(P8) in the graph shown in FIG. 8C,which illustrates Data 810 and f(E) 815. The population follows a Fermifunction f(E) as the chemical potential of the dot level can be loweredpast the Fermi level of the lead. The data shown in the graph of FIG. 8Ccan be nicely fit to a Fermi function with an electron temperatureT_(e)=120 mK.

An exemplary detailed analysis of the real-time single electrontunneling events can be used to determine the charge sensorsignal-to-noise ratio (“SNR”) and sensitivity. A one-second time seriesof the current through the charge sensor with dot 8 tuned to the N₈=0 to1 charge degeneracy point can be measured. The data can be acquired at asampling rate of about 500 kHz and a Kaiser-Bessel finite impulseresponse (“FIR”) filter can be used to reduce the effective measurementbandwidth to about 30 kHz. An about 30 ms long segment of this timeseries is shown in the exemplary graph of FIG. 9A. Real time tunnelingevents between N₈=0 (e.g., element 905) and N₈=1 (e.g., element 910) areseen as two level switching in the measured current. A histogram of thefull time trace is shown in the graph of FIG. 9B. The two well-resolvedpeaks correspond to the two charge states. Each peak can be nicely fitto a Gaussian with width σ₁=0.112 nA, corresponding to the current noisein the exemplary measurement setup. The centroids of the two Gaussianscan be separated by ΔI=0.772 nA, which can correspond to the signalassociated with a change in electron occupancy of one. For these data, aSNR=ΔI/σ₁=6.9 can be extracted. By adjusting the FIR filter cutofffrequency, f, the SNR can be plotted as a function of the effectivemeasurement bandwidth in the graph shown in FIG. 9C, which illustratesthat the SNR decreases with increasing f.

A quantitative description of the SNR can benefit from a more carefulanalysis of the experimental setup. Thus, the current noise of theexemplary device can be measured. The measured noise spectra, i_(n) (f),at current levels of about 4 nA (e.g., about 6 nA) are plotted as thetraces 915 and 920 in the inset of the graph illustrated in FIG. 9C. Thenoise can be approximately white at high frequencies, but noise with anapproximate 1/f dependence can dominate at low frequency, and theoverall noise level appears to be correlated to the derivative of thecharge sensor current with respect to gate voltage. These spectra can beused to calculate the expected noise for a one second time series byintegrating over frequency from 1 Hz to the filter cutoff frequency, f,which can produce, for example:σ₁ ²(f)=∫_(1 Hz) ^(f) i _(n) ²(f′)df′.  (1)

Using the measured signal ΔI=0.772 nA, the expected SNR can be plottedas a function of f in the graph shown in FIG. 9C. The measured SNR fallswithin the shaded region 925 between the two curves 930 and 935, whichdelineate the expected SNR for current levels of 4 and 6 nA. For a 30kHz bandwidth the SNR=7, implying an effective charge sensitivity of8.2×10⁻⁴ e/√{square root over (Hz)}. This sensitivity can be favorableto both the rf−QPC (˜10⁻³ e/√{square root over (Hz)}) (see, e.g.,Reference 32) and dispersive gate readout (6.3×10⁻³ e/√{square root over(Hz)}) (see, e.g., Reference 33), however the exemplary measurementbandwidth can be limited to about 30 kHz due to the exemplary currentamplifier. Improvements in both the sensitivity and measurementbandwidth can be facilitated by using a low temperature preamplifier(see, e.g., Reference 34) and a higher bandwidth room temperatureamplifier.

Exemplary Versatility

The exemplary 9 dot linear array can be capable of hosting a diverserange of quantum dot qubits. Using individual spins, ninenearest-neighbor exchange-coupled Loss-DiVincenzo qubits can be formedwithin the exemplary array. (See, e.g., Reference 10). With the gatevoltages configured differently, four singlet-triplet qubits can beformed using pairs of electrons (see, e.g., Reference 2) and the qubitscan be coupled via a dipole-dipole interaction. Additionally, threeexchange-only spin qubits can be defined, facilitating full electricalcontrol over the Bloch sphere of each qubit. (See, e.g., References 26,35 and 36). To demonstrate the versatility of this exemplary devicearchitecture, a single-shot readout of an electron spin can be shown.Two capacitively-coupled DQD charge qubits can be formed, and aninteraction strength of about 200 μeV can be measured, which can providean about 50 GHz two-qubit gate operation speed.

A single shot spin state readout on dot 8 in the linear array can beshown. A three-step pulse sequence can be employed to measure the spinrelaxation time T₁ at a magnetic field B=1 T. (See, e.g., References 23and 24). Starting with an empty dot, the chemical potential of the dotlevel can be plunged below the Fermi level of the lead, which canfacilitate an electron to load into either the spin up or the spin downstate. After a time t_(wait), the readout phase can begin by setting thechemical potential of the dot such that the spin up and spin down energylevels can straddle the Fermi level of the lead. If the electron on thedot can be in the spin-up excited state, as shown in the diagram of FIG.10A, the electron can hop off of the dot and be replaced by a spin-downelectron. The change in the charge occupancy of the quantum dot due tothis process can be visible in time series measurements of the sensordot current, I, and can be referred to as a “spin bump.” In contrast, ifthe final spin state can be spin down, no spin bump may be observed.Then, the chemical potential of both spin states can be raised above theFermi level to empty the dot and complete the measurement cycle.

Exemplary single shot traces are shown in the graph of FIG. 10B. Spin upelectrons are indicated in FIG. 10B by current pulses during the readoutphase (e.g., traces 1005), while spin down electrons simply remain onthe dot during the readout phase (e.g., traces 1010). T₁ can beextracted by varying t_(wait) and measuring the probability P_(↑) ofbeing in the spin up state at the end of the measurement phase. (See,e.g., graph of FIG. 10C). Each data point 1015 can represent the averageof 10,000 single shot traces. The resulting data can be fit to anexponential decay with a best fit T₁=170±17 ms. The long spin relaxationtime can be a defining factor of the Si “semiconductor vacuum.”

Capacitive coupling has been proposed to mediate two qubit interactions.(See, e.g., Reference 12). The exemplary compact gate design can lead tolarge capacitive couplings. For example, the capacitive coupling of twoadjacent DQDs was investigated. Dots 6-7 can be used to define one DQD,and dots 8-9 to define a second DQD. The charge stability diagrams forthese DQDs are shown in the graphs of FIGS. 11A and 11B. The barriergate voltage VB8 can be set such that there may be no tunneling betweendots 7 and 8. As a result, the two DQDs can optionally be coupled onlyvia a capacitive interaction C_(m). Interdot detuning axes, ε_(L) andε_(R), are overlaid on the data in the graphs of FIGS. 11A and 11B. Bysweeping ε_(L) vs ε_(R), the quadruple quantum dot stability diagramshown in FIG. 11C can be obtained. The mutual capacitance C_(m) causesthe (N₆, N₇)=(1,0) to (0,1) interdot charge transition can shift byΔε_(L)=0.77 when the occupancy of the second DQD can change from (N₈,N₉)=(1,0) to (0,1). Using the lever-arm conversion between gate voltageand energy, this can correspond to an about 200 μeV energy shift (e.g.,about 50 GHz two-qubit gate operation time). (See, e.g., Reference 37).

The exemplary device according to an exemplary embodiment of the presentdisclosure can be a scalable quantum dot gate architecture that canyield quantum dots with uniform and reproducible characteristics. Anexemplary 12 quantum dot device can include a linear array of ninequantum dots and three single quantum dot charge sensors can beprovided. From characterization measurements, standard deviations in thecharging energies and orbital energies of less than about 20% relativeto their means: E_(c)=6.9±0.7 meV, E_(orb)=3.0±0.5 meV can be obtained.

The exemplary device can detect real-time tunneling events in this largearray, and use this capability for single shot measurements of theelectron spin. The dipole-dipole coupling of two adjacent DQDs formed inthe array can be characterized, and an interaction energy of 200 μeV,can be measured, which bodes well for computing architectures that relyon capacitive coupling of qubits.

According to certain exemplary embodiments of the present disclosure,for example, a quantum dot device can be provided, which can include afirst aluminum layer configured to operate as a screening layer, asecond aluminum layer, associated with the first aluminum layer, andconfigured to accumulate electrons in the a two-dimensional electrongas, and a third aluminum layer configured to tune a barrier(s) betweenregions of a two-dimensional electron gas accumulated by the secondaluminum layer. The first, second and third aluminum layers can befabricated or provided on an undoped silicon/silicon-germanium (Si/SiGe)substrate. Each of the first, second and third aluminum layers can havethereon a thin oxide layer. The thin oxide layer can be formed byexposing the first, second and third aluminum layers to an oxygen/argonmixture in a vacuum after metallization, and the thin oxide layer canelectrically isolate one of the first, second and third aluminum layersfrom another of the first second and third aluminum layers.

In some exemplary embodiments of the present disclosure, the firstaluminum layer can include a single-dimensional channel that can have anarray of quantum dots. The first aluminum layer can include a pluralityof transport channels adjacent to the single-dimensional channel, whereeach of the transport channels can include a single charge sensingquantum dot. The second aluminum layer can include a plurality of gatesdisposed thereon. The gates can be held at a relatively positivevoltage, and the gates can accumulate electrons through a plurality ofopenings in the first aluminum layer.

A further exemplary embodiment of the present disclosure can include,for example, a method for fabricating a quantum dot device, which caninclude, forming a first aluminum layer, where the first aluminum layercan be configured to operate as a screening layer, forming a secondaluminum layer adjacent to the first aluminum layer, where the secondaluminum layer can be configured to accumulate electrons, and forming athird aluminum layer adjacent to the second layer, where the thirdaluminum layer can be configured to tune a barrier(s) between regions ofa two-dimensional electron gas (2DEG) accumulated by the second aluminumlayer. The first, second and/or third aluminum layers can each be formedon an undoped silicon/silicon-germanium (Si/SiGe) substrate. A thinoxide layer can be formed on each of the first, second and thirdaluminum layers, which can be formed by exposing the first, second andthird aluminum layers to an oxygen/argon mixture in a vacuum aftermetallization.

In certain exemplary embodiments of the present disclosure, asingle-dimensional channel that has an array of quantum dots can beformed or otherwise provided on the first aluminum layer. A plurality oftransport channels can be formed on the first aluminum layer, adjacentto the single-dimensional channel, where each of the transport channelscan include a plurality of charge sensing quantum dots. A plurality ofgates can be formed or otherwise provided on the second aluminum layer,where the gates can be held at a relatively positive voltage. The gatescan accumulate electrons through a plurality of openings in the firstaluminum layer. The second aluminum layer can be formed on top of thefirst aluminum layer, and the third aluminum layer can be formed on topof the second aluminum layer.

FIG. 12 shows an exemplary method 1200 for fabricating a quantum dotdevice, according to an exemplary embodiment of the present disclosure.For example, at procedure 1205, a first conductive layer, e.g. aluminum,can be formed. In some exemplary embodiments of the device this can bedone using electron-beam lithography, photolithography, and/or metalevaporation. At procedure 1210, an insulating layer can be formed inorder to electrically isolate the first conductive layer. At procedure1215, a second conductive layer can be formed, and at procedure 1220 asecond insulating layer can be formed in order to electrically isolatethe second conductive layer. Procedure 1215 and 1220 can be executedusing a similar processes and conductive materials, e.g. aluminum, asprocedures 1205 and 1220 or by using different materials and processes.At procedure 1225 a third conductive layer can be formed on top, oradjacent to the first two layers. These conductive and insulatinglayers, and any gate structures within them can be used to createquantum dots by applying different or similar voltages to them 1230.

FIG. 13 shows a block diagram of an exemplary embodiment of a systemaccording to the present disclosure. For example, exemplary proceduresin accordance with the present disclosure described herein can beperformed by a processing arrangement and/or a computing arrangement1302. Such processing/computing arrangement 1302 can be, for exampleentirely or a part of, or include, but not limited to, acomputer/processor 1304 that can include, for example one or moremicroprocessors, and use instructions stored on a computer-accessiblemedium (e.g., RAM, ROM, hard drive, or other storage device).

As shown in FIG. 13, for example a computer-accessible medium 1306(e.g., as described herein above, a storage device such as a hard disk,floppy disk, memory stick, CD-ROM, RAM, ROM, etc., or a collectionthereof) can be provided (e.g., in communication with the processingarrangement 1302). The computer-accessible medium 1306 can containexecutable instructions 1308 thereon. In addition or alternatively, astorage arrangement 1310 can be provided separately from thecomputer-accessible medium 1306, which can provide the instructions tothe processing arrangement 1302 so as to configure the processingarrangement to execute certain exemplary procedures, processes andmethods, as described herein above, for example.

Further, the exemplary processing arrangement 1302 can be provided withor include an input/output arrangement 1314, which can include, forexample a wired network, a wireless network, the internet, an intranet,a data collection probe, a sensor, etc. As shown in FIG. 13, theexemplary processing arrangement 1302 can be in communication with anexemplary display arrangement 1312, which, according to certainexemplary embodiments of the present disclosure, can be a touch-screenconfigured for inputting information to the processing arrangement inaddition to outputting information from the processing arrangement, forexample. Further, the exemplary display 1312 and/or a storagearrangement 1310 can be used to display and/or store data in auser-accessible format and/or user-readable format.

The foregoing merely illustrates the principles of the disclosure.Various modifications and alterations to the described embodiments willbe apparent to those skilled in the art in view of the teachings herein.It will thus be appreciated that those skilled in the art will be ableto devise numerous systems, arrangements, and procedures which, althoughnot explicitly shown or described herein, embody the principles of thedisclosure and can be thus within the spirit and scope of thedisclosure. Various different exemplary embodiments can be used togetherwith one another, as well as interchangeably therewith, as should beunderstood by those having ordinary skill in the art. In addition,certain terms used in the present disclosure, including thespecification, drawings and claims thereof, can be used synonymously incertain instances, including, but not limited to, for example, data andinformation. It should be understood that, while these words, and/orother words that can be synonymous to one another, can be usedsynonymously herein, that there can be instances when such words can beintended to not be used synonymously. Further, to the extent that theprior art knowledge has not been explicitly incorporated by referenceherein above, it is explicitly incorporated herein in its entirety. Allpublications referenced are incorporated herein by reference in theirentireties.

EXEMPLARY REFERENCES

The following references are hereby incorporated by reference in theirentireties:

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What is claimed is:
 1. A quantum dot device, comprising: at least threeconductive layers comprising: a first conductive layer configured tooperate as a screening layer, a second conductive layer configured tocause accumulation of electrons in a two-dimensional electron gas(2DEG), and a third conductive layer configured to tune at least onebarrier between regions of the 2DEG; and at least two insulating layers,wherein a first one of the insulating layers electrically insulates thefirst conductive layer from the second conductive layer, and a secondone of the insulating layers electrically insulates the secondconductive layer from the third conductive layer.
 2. The quantum dotdevice of claim 1, wherein one of the at least three conductive layersis composed of a different material than the other two of the at leastthree conductive layers.
 3. The quantum dot device of claim 1, whereinthe at least three conductive layers are composed of the same material.4. The quantum dot device of claim 3, wherein the material is at leastone of (i) aluminum, (ii) gold, (iii) copper or (iv) polysilicon.
 5. Thequantum dot device of claim 1, wherein the at least three conductivelayers are at least partially composed of at least one of (i) aluminum,(ii) gold, (iii) copper or (iv) polysilicon.
 6. The quantum dot deviceof claim 1, wherein the at least two insulating layers are composed ofat least one of (i) silicon oxide, (ii) silicon nitride or (iii)aluminum oxide.
 7. The quantum dot device of claim 1, wherein the atleast three conductive layers are composed of a metallic material havinga purity rate of over 90%.
 8. The quantum dot device of claim 1, whereineach of the at least three conductive layers has a thickness of lessthan about 200 nm.
 9. The quantum dot device of claim 8, wherein each ofthe at least three conductive layers has a thickness of less than about100 nm.
 10. The quantum dot device of claim 1, wherein each of the atleast two insulating layers has a thickness of less than about 10 nm.11. The quantum dot device of claim 10, wherein each of the at least twoinsulating layers has a thickness of less than about 4 nm.
 12. Thequantum dot device of claim 1, wherein each of the at least twoinsulating layers is in direct contact with two of the at least threeconductive layers.
 13. The quantum dot device of claim 1, furthercomprising: at least three further conductive layers; and at least twofurther insulating layers electrically insulating the at least threefurther conductive layers from one another, wherein the at least threefurther conductive layers are electrically coupled to the at least threeconductive layers.
 14. The quantum dot device of claim 1, wherein the atleast three conductive layers are fabricated or provided on asemiconductor substrate.
 15. The quantum dot device of claim 1, whereingate electrodes defined in each of the at least three conductive layersinclude a different voltage level applied therethrough.
 16. The quantumdot device of claim 1, wherein connections between the conductive layersand the insulating layers causes single electrons to be shuttled throughquantum dots of the device using voltage pulses.
 17. The quantum dotdevice of claim 1, wherein the first conductive layer comprises a firstchannel configured for forming a plurality of quantum dots and a secondchannel configured for forming a sensor quantum dot for reading valuesof the plurality of quantum dots.
 18. The quantum dot device of claim17, wherein the second conductive layer comprises a first plurality ofconductive gates configured to control a number of electrons incorresponding quantum dots of the plurality of quantum dots, and whereinthe third conductive layer comprises a second plurality of gatesconfigured to control tunnel coupling between corresponding adjacentquantum dots of the plurality of quantum dots.
 19. A quantum dot device,comprising: at least three conductive layers comprising: a firstconductive layer configured to operate as a screening layer, a secondconductive layer configured to cause accumulation of electrons in atwo-dimensional electron gas (2DEG), and a third conductive layerconfigured to tune at least one barrier between regions of the 2DEG; andat least two insulating layers, wherein a first one of the insulatinglayers electrically insulates the first conductive layer from the secondconductive layer and the third conductive layer, and a second one of theinsulating layers electrically insulates the second conductive layerfrom the third conductive layer.
 20. The quantum dot device of claim 19,wherein one of the at least three conductive layers is composed of adifferent material than the other two of the at least three conductivelayers.
 21. The quantum dot device of claim 19, wherein the at leastthree conductive layers are composed of the same material.
 22. Thequantum dot device of claim 19, wherein the at least three conductivelayers are at least partially composed of at least one of (i) aluminum,(ii) gold, (iii) copper or (iv) polysilicon.
 23. The quantum dot deviceof claim 19, wherein the at least two insulating layers are composed ofat least one of (i) silicon oxide, (ii) silicon nitride or (iii)aluminum oxide.
 24. The quantum dot device of claim 19, furthercomprising: at least three further conductive layers; and at least twofurther insulating layers electrically insulating the at least threefurther conductive layers from one another, wherein the at least threefurther conductive layers are electrically coupled to the at least threeconductive layers.
 25. The quantum dot device of claim 19, whereinconnections between the conductive layers and the insulating layerscauses single electrons to be shuttled through quantum dots of thedevice using voltage pulses.
 26. The quantum dot device of claim 19,wherein the first conductive layer comprises a first channel configuredfor forming a plurality of quantum dots and a second channel configuredfor forming a sensor quantum dot for reading values of the plurality ofquantum dots.
 27. The quantum dot device of claim 26, wherein the secondconductive layer comprises a first plurality of conductive gatesconfigured to control a number of electrons in corresponding quantumdots of the plurality of quantum dots, and wherein the third conductivelayer comprises a second plurality of gates configured to control tunnelcoupling between corresponding adjacent quantum dots of the plurality ofquantum dots.